HEF40373B

File under Integrated Circuits, IC04

January 1995

Philips SemiconductorsProduct specification

Octal transparent latch with 3-state outputs

DESCRIPTION

The HEF40373B is an 8-bit transparent latch with 3-statebuffered outputs. The output stages have high currentoutput capability suitable for driving highly capacitiveloads. The latch outputs follow the data inputs when thelatch enable (E) is HIGH. When E is LOW, the data thatmeets the set-up times is latched. The 3-state outputs arecontrolled by the output enable inputEO. A HIGH on

HEF40373B

MSI

EOcauses the outputs to assume a high impedanceOFF-state. The device features hysteresis on the E inputto improve noise rejection.

Schmitt-trigger action in the E input makes the circuithighly tolerant to slower input rise and fall times.The HEF40373B is pin and functionally compatible withthe TTL ‘373’ device.

Supply voltage range: 3 to 15 V.

Fig.1 Functional diagram.Fig.2 Pinning diagram.PINNING

HEF40373BP(N):20-lead DIL; plastic

(SOT146-1)

HEF40373BD(F):HEF40373BT(D):

20-lead DIL; ceramic (cerdip)(SOT152)20-lead SO; plastic(SOT163-1)

(): Package Designator North America

FAMILY DATA, IDDLIMITScategoryMSISee Family SpecificationsD0to D7EEOO0to O7

data inputslatch enable input

output enable input (active LOW)3-state buffered outputs

January 19952

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Octal transparent latch with 3-state outputs

FUNCTION TABLE

OPERATING MODESenable & read registerlatch & read registerlatch register & disable outputsNotes

1.H=HIGH state (the more positive voltage)

h=HIGH state (one set-up time prior to the HIGH-to-LOW enable transition)L=LOW state (the less positive voltage)

I=LOW state (one set-up time prior to the HIGH-to-LOw enable transition)Z=high impedance OFF-state

INPUTSEOLLLLHHEHHLLLLDnLHIhIhINTERNALREGISTERLHLHLHHEF40373B

MSI

OUTPUTSO0TO O7LHLHZZJanuary 199

Philips SemiconductorsProduct specification

Octal transparent latch with 3-state outputs

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)See Family Specifications, except for:D.C. current into any input

D.C. source or sink current into any outputD.C. current into the supply terminalsDC CHARACTERISTICSVSS=0 V

VDDVVOHVVOLVSYMBOLTamb(°C)−40MIN.Output currentHIGHOutput currentHIGHOutput currentLOWHysteresisvoltage atenable input (E)51015510155101551015VH4,69,513,53,68,413,20,40,51,5IOL−IOH−IOH0,751,8514,59,314,419,52,99,530,0TYP.+25MIN.0,61,5151015202,37,625TYP.1,23,0502446625,41745220250320±II±IO±I

max.max.max.

HEF40373B

MSI

10mA25mA100mA

+85MIN.0,451,115,510,715,019,81,755,5019,0TYP.mAmAmAmAmAmAmAmAmAmVmVmV(1)P-channel MOS transistor conducting.(2)P-channel MOS transistor and bipolarn-p-n transistor conducting.Fig.5 Typical output source current characteristic.Fig.6 Schematic diagram of output stage.January 19955

Philips SemiconductorsProduct specification

Octal transparent latch with 3-state outputs

AC CHARACTERISTICS

VSS=0 V; Tamb=25°C; CL=50 pF; input transition times≤20 ns

VDDVPropagation delaysE→OnHIGH to LOWE→OnLOW to HIGHOutput transitiontimesHIGH to LOWLOW to HIGH3-state propagation delaysOutput disable timesEO→OnHIGH510155LOWOutput enable timesEO→OnHIGH510155LOWSet-up timeDn→EHold timeDn→EMinimum latch enablepulse width LOW1015510155101551015tWELtholdtsu151010251510603020tPZLtPZH6530258535257551330151013060501707050nsnsnsnsnsnsnsnsnsnsnsnsnsnsns1015tPLZtPHZ653025703013060501508060nsnsnsnsnsns51015510155101551015tTLHtTHLtPLHtPHL150604012550404020153020153001208025010080804030604030nsnsnsnsnsnsnsnsnsnsnsnsSYMBOLMIN.TYP.MAX.HEF40373B

MSI

TYPICAL EXTRAPOLATIONFORMULA138 ns+(0,24 ns/pF) CL59 ns+(0,01 ns/pF) CL36 ns+(0,07 ns/pF) CL122 ns+(0,06 ns/pF) CL48 ns+(0,03 ns/pF) CL39 ns+(0,02 ns/pF) CLsee Fig.7January 19956

Philips SemiconductorsProduct specification

Octal transparent latch with 3-state outputs

AC CHARACTERISTICS

VSS=0 V; Tamb=25°C; input transition times≤20 ns

VDDVDynamic powerdissipation perpackage (P)51015TYPICAL FORMULA FOR P (µW)3 325 fi+∑(foCL)×VDD214 200 fi+∑(foCL)×VDD237 425 fi+∑(foCL)×VDD2whereHEF40373B

MSI

fi=input freq. (MHz)fo=output freq. (MHz)CL=load capacitance (pF)∑(foCL)=sum of outputsVDD=supply voltage (V)tTLH−−−− tTHLFig.7 Output transition times as a function of the load capacitance. .January 19957