KS8803B 10/15 CH PLL
INTRODUCTION
16-DIP-300AThe KS8803B/4B are designed to select 10/15 channelsof cordlss phone of which frequency band is 46/49MHz.It has reference frequency generator, programmable divid-er for transmit and receive section and phase detector.
16-SOP-225FEATURES
•10 Channels selectable : KS8803B(both transmit/receive)
•15 Channels selectable : KS8804B(both transmit/receive)
•Include oscillation circuit with external x-tal(10.24MHz)
•5KHz output for guard tone•Unlock detector
(phase difference more than 6.25us)•Stand-by function for power saving
ORDERING INFORMATION
DeviceKS8803BKS8803BD
Package 16-DIP-300A 16-SOP-225
Operating Temperature
- 30°C ~ + 75°C
BLOCK DIAGRAM
VDD
VSS
1512
+V
DD
OSC IN
16111
PHASEDETECTOR (Tx)
REFERENCEDIVIDER
4
F1
OSC OUT
PDT
PHASEDETECTOR (Rx)13
PDR
TIF
9
PROGRAMMABLEDIVIDER (Tx)PROGRAMMABLEDIVIDER (Rx)
14
+RIF
DECODER
UNLOCKDETECTOR
10
LDT
3
SB
5
D0
6
D1
7
D2
82
D3MODE
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KS8803B 10/15 CH PLL
PIN CONFIGURATION
OSC OUT
1234
KS8803B5678
161514131211109
OSC IN
MODEVDD
SBRIF
F1PDR
D0VSSPDT
D1
D2LDT
D3TIF
PIN DESCRIPTION
Pin NoSymbolDescription •This output generates reference frequency1OSC OUT when it is connected to Pin 16 with external OSC of which frequency is 10.24MHz • Base/Remote Unit Selection Pin2MODE “High” : Base Unit “Low” : Remote Unit • Stand-by pin • This input controls Tx PLL for reducing3SB the power dissipation “High” : Normal operation “Low” : Stand-by45678F1D0D1D2D3 • Input to programmable divider of Tx9TIF • AC coupling with VCO • In case of lager signal, It needs DC-coupling • Min. input voltage is 0.1Vrms10LDT • Unlocked signal out pin (see output charateristics) • 5KHz output • Channel selection pins • The Combinations of these inputs select one channel among the 10/15 channels元器件交易网www.cecb2b.com
KS8803B 10/15 CH PLL
PIN DESCRIPTION
Pin No
Symbol
• Phase detector output for Tx
11
PDT
• PDT detects the phase error from Tx PLLand its output is connected to external lowpass filter
12
VSS
• This pin is negative supply of the IC.• It usually grounded
• Phase detector output for Rx
13
PDR
• PDR detects the phase error from Rx PLLand its output is connected to external lowpass filter
• Input of programmable divider for Rx.• AC coupling with VCO
14
RIF
• In case of lager signal (standard CMOSlogic), it needs DC coupling• Min. input voltage is 0.1Vrms• This pin is positive supply of the IC
15
VDD
• Its reference is VSS, and normally + 3.0V ~ + 5.5V more positive than VSS• X-TAL osc connection pin
16
OSC IN
• This input generates the reference frequencywhen it is connected to pin 1 with externalosc
Description
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KS8803B 10/15 CH PLL
ABSOLUTE MAXIMUM RATING ES (Ta = 25°C)
Characteristic
Supply voltageInput VoltagePower DissipationOperating TemperatureStorage Temperature
SymbolVDDVIPDTOPRTSTG
Value- 0.5 ~ 6.0- 0.3 ~ VDD + 0.5
350- 30 ~ + 75- 40 ~ + 125
UnitVVmW°C°C
ELECTRICAL CHARACTERISTICS (Ta = 25°C, VDD = 5V, unless otherwise specitied)
CharacterostocSupply VoltageSymbolVDDVIH1Input VoltageVIL1VIH2VIL2fI1Input Frequencyfl2fI3VI(AMP)1Input AmplitudeVI(AMP)2VI(AMP)3Input CurrentIIHIILD0 - D3, SBD0 - D3, SBMODEMODEVTIF = 0.15VrmsVRIF = 0.15VrmsOSCIN = 0.3VrmsfTIF = 52MHzfRIF = 42MHzOSCIN = 11MHzVIN = VDDVIN = VSSTest Conditions-Min30.7VDD-0.9VDD-103050.10.10.3--Typ-------10.24-----Max5.5VDD0.3VDDVDD0.1VDD5242110.3VDD0.3VDD0.3VDD4040UnitVVVVVMHzMHzMHzVrmsVrmsVrmsµAµA元器件交易网www.cecb2b.com
KS8803B 10/15 CH PLL
ELECTRICAL CHARACTERISTICS (Ta = 25°C, VDD = 5V, unless otherwise specified)
CharacteristicSymbolVOH1Output VoltageVOL1VOH2VOL2Output OFF LeakageCurrentStand-by CurrentILKG1ILKG2ISB1ISB2IDD1IDD2Test ConditionsPDT, RDR : IO = 0.5mAPDT, RDR : IO = 0.5mALDT : IO = 1mAF1 : IO = 1mAPDT, PDR : VO = VDD/VSSLDT : VO = VSSVDD = 3V (Note 2)VDD = 3V (Note 2)VDD = 3V (Note 1)VDD = 5V (Note 1)MinVDD-1.0-VDD-1.0----3.5--Typ----0.01-1.04.02.06.0Max-1.0-1.01.05.02.0-3.07.0UnitVVVVµAµAmAmAmAmAOperating Current• NOTE 1) OSCIN
TIFRlFMODE• NOTE 2) OSCIN
TlFRIFMODE
: 10.24MHz X-tal Connection: 27MHz 150mVrms: 42MHz 150mVrrns
: VDD, SB = VDD, others are opened: 10.24MHz X-tal Connection: 27MHz 150rnVrms: 42MHz 150mVrms
: VDD, SB = VSS, others are opened
• Capacitor more than 2000pF should be connected between VDD & VSS
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KS8803B 10/15 CH PLL
OUTPUT CHARACTERISTICS
1) LOCK
tPDtPDtPD : Phase Difference ( 6.25µs )VDDVSSVDDVSSFloatingVDDVSSVDDVSS6.4msVDDFloatingReference DividerProgrammableDividerLDT2) UNLOCKReference DividerProgrammableDividerLDT元器件交易网www.cecb2b.com
KS8803B 10/15 CH PLL
TABLE 1. Channel & Frequency table to Base/Remote input data tor KS8803B (10CH)BASE (MODE = 1)
INPUT
D0 D1 D2 D31 0 0 00 1 0 01 1 0 00 0 1 01 0 1 00 1 1 01 1 1 00 0 0 11 0 0 10 1 0 11 1 0 10 0 1 11 0 1 10 1 1 11 1 1 10 0 0 0
CH12345678910101010101010
fRX(MHz)49.67049.84549.86049.77049.87549.83049.89049.93049.99049.97049.97049.97049.97049.97049.97049.970
Rx (fREF = 5KHz)fVCO(MHz)38.97539.15039.16539.07539.18039.13539.19539.23539.29539.27539.27539.27539.27539.27539.27539.275
N7795783078337815783678277839784778597855785578557855785578557855
fTX(MHz)46.61046.63046.67046.71046.73046.77046.83046.87046.93046.97046.97046.97046.97046.97046.97046.970
Tx (fREF = 5KHz)
fVCO(MHz)46.61046.63046.67046.71046.73046.77046.83046.87046.93046.97046.97046.97046.97046.97046.97046.970
N9322932693349342934693549366937493869394939493949394939493949394
REMOTE (MODE = 0)
INPUT
D0 D1 D2 D31 0 0 00 1 0 01 1 0 00 0 1 01 0 1 00 1 1 01 1 1 00 0 0 11 0 0 10 1 0 11 1 0 10 0 1 11 0 1 10 1 1 11 1 1 10 0 0 0
CH12345678910101010101010
fRX(MHz)46.61046.63046.67046.71046.73046.77046.83046.87046.93046.97046.97046.97046.97046.97046.97046.970
Rx (fREF = 5KHz)fVCO(MHz)35.91535.93535.97536.01536.03536.07536.13536.17536.23536.27536.27536.27536.27536.27536.27536.275
N7183718771957203720772157227723572477255755572557255725572557255
fRX(MHz)49.67049.84549.86049.77049.87549.83049.89049.93049.99049.97049.97049.97049.97049.97049.97049.970
Tx (fREF = 5KHz)fVCO(MHz)49.67049.84549.86049.77049.87549.83049.89049.93049.99049.97049.97049.97049.97049.97049.97049.970
N9934996999729954997599669978998699989994999499949994999499949994
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KS8803B 10/15 CH PLL
TABLE 2. Channel & Frequency table to Base/Remote input data tor KS8804B (15CH)BASE (MODE = 1)
INPUT
D0 D1 D2 D31 0 0 00 1 0 01 1 0 00 0 1 01 0 1 00 1 1 01 1 1 00 0 0 11 0 0 10 1 0 11 1 0 10 0 1 11 0 1 10 1 1 11 1 1 10 0 0 0
CH12345678910111213141515
fRX(MHz)49.69549.71049.72549.74049.75549.67049.84549.86049.77049.87549.83049.89049.93049.99049.97049.970
Rx (fREF = 5KHz)fVCO(MHz)39.00039.01539.03039.04539.06038.97539.15039.16539.07539.18039.13539.19539.23539.29539.27539.275
N7800780378067809781277957830783378157836782778397847785978557855
fTX(MHz)46.51046.53046.55046.57046.59046.61046.63046.67046.71046.73076.77046.83046.87046.93046.97046.970
Tx (fREF = 5KHz)
fVCO(MHz)46.51046.53046.55046.57046.59046.61046.63046.67046.71046.73046.77046.83046.87046.93046.97046.970
N9302930693109314931893229326933493429346935493669374938693949394
REMOTE (MODE = 0)
INPUT
D0 D1 D2 D31 0 0 00 1 0 01 1 0 00 0 1 01 0 1 00 1 1 01 1 1 00 0 0 11 0 0 10 1 0 11 1 0 10 0 1 11 0 1 10 1 1 11 1 1 10 0 0 0
CH12345678910111213141515
fRX(MHz)46.51046.53046.55046.57046.59046.61046.63046.67046.71046.73076.77046.83046.87046.93046.97046.970
Rx (fREF = 5KHz)fVCO(MHz)35.81535.83535.85535.87535.89535.91535.93535.97536.01536.03536.07536.13536.1753623536.27536.275
N7163716771717175717971837187719572037207721572277235724772557255
fRX(MHz)49.69549.71049.72549.74049.75549.67049.84549.86049.77049.87549.83049.89049.93049.99049.97049.970
Tx (fREF = 5KHz)fVCO(MHz)49.69549.71049.72549.74049.75549.67049.84549.86049.77049.87549.83049.89049.93049.99049.97049.970
N9939994299459948995199349969997299549975996699789986999899949994
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KS8803B 10/15 CH PLLAPPLICATION CIRCUITANTBPF46.610MHz ( R )49.670MHz ( B )49.670MHz ( R )46.610MHz ( B )1’stMIX10.695MHz2’ndMIX39.915MHz38.975MHz ( B )TXVCO+455KHz10.24MHzBPF( R ) : REMOTE UNIT( B ) : BASE UNITRXVCO+VDDto MICOM( Unlock Detect )1615ProgrammableDivider ( RX )1413PhaseDetector ( RX )1211109PhaseDetector ( TX )ProgrammableDivider ( TX )REF.DIVIDERDECODER1X - TAL10.24MHzVDDBASEREMOTE2345678to MICOM( D0, D1, D2, D3 )5.0KHzVDD : TX PLL ENABLEVSS : TX PLL DISABLE
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