Quartus中fft_ip_core的使用

在论坛中经常有人会问起altera软件fft ip中使用方法，有些人在使用这个fft ip core的时候没有得到正确的结果，事实上，这个ip core还是比较容易使用的。有些人得不到正确的仿真结果可能是没有设定足够的仿真时间，如果控制信号设定正确的话，一般情况下，可以设定3-4帧的仿真时间就可以看到正确的结果了。另外一些人是没有处理好fft ipcore的一些输入信号而得不到正确结果的。要使用好这个ip core主要处理好以下些信号： 1、 sink_sop：用来指示每帧输入数据的第一个数据 2、 sink_eop：用来指示每帧输入数据的最后一个数据 3、 sink_valid：每帧输入数据有效时为高电平

可以采用状态机来控制这些信号，或者也可以采用一个计数器来产生这些信号，用以满足fft ip core的信号要求。

Ff t ip core有多种工作模式，其中burst data模式耗用的资源最少，但处理的时间也最长。下面我就以这个ipcore的burst data为例给大家说明一下用fft ipcore来进行256点的fft运算。使用的软件为quartusII8.0sp1，仿真工具为modelsim se plus 6.4

1、 首先，新建一下工程，比如工程的名称为fft256（怎么建工程不用我再说了吧），器件选

择cyclone的ep1c3t144c8（因为手上有这个片子的板子，所以就选了它），如图1-1所示

图1-1 选择器件

2、 使用MegeWizard Plug-in Manager…来设定fft，依次进行参数设定，仿真设定及生成操

作。

a、 参数选择，器件选cyclone，变换长度选256如图1-2如示，fft engine architecture

选择single output,number选1，I/O data flow选burst如图1-3如示，其它例化选项

用缺省值如图1-4如示

图1-2 设定参数

图1-3 设定结构

图1-4 例化选项

b、 仿真设定，如图1-5所示，如果不是正式使用的license的话，可能不会生成netlist

图1-5 设定仿真

c、 生成ipcore

3、 用状态机控制生成sink_sop, sink_eop, sink_valid等信号（ctrl_fft.vhd），具体程序如下： library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; entity ctrl_fft is port( reset_n : in std_logic; clk : in std_logic; sink_ready : in std_logic; sink_sop : out std_logic; sink_eop : out std_logic; sink_valid : out std_logic); end ctrl_fft;

architecture one of ctrl_fft is

constant frame : integer := 256; --fft点数 type state is (idle,go,assert_eop,wait_state); signal current_state,next_state : state;

signal count,next_count : integer range 0 to frame - 1; signal sink_sop_d,sink_eop_d,sink_valid_d : std_logic; begin

process(current_state,sink_ready,count) begin case current_state is when idle => next_count <= 0; if (sink_ready = '1') then next_state <= go; else next_state <= idle; end if; when go => if (count < frame - 2) then next_state <= go; next_count <= count + 1; else next_state <= assert_eop; next_count <= count + 1; end if; when assert_eop => next_count <= 0; next_state <= wait_state; when wait_state => if (sink_ready = '1') then next_count <= 0; next_state <= go;

else

next_count <= count ; next_state <= wait_state; end if; end case; end process;

sink_sop_d<='1' when ((next_state=go) and (next_count=0)) else '0'; sink_eop_d<='1' when (next_state=assert_eop) else '0';

sink_valid_d<='1' when ((next_state=go) or (next_state=assert_eop)) else '0'; process(reset_n,clk) begin

if (reset_n = '0') then current_state <= idle; count <= 0; sink_sop <= '0'; sink_eop <= '0'; sink_valid <= '0'; elsif rising_edge(clk) then current_state <= next_state; count <= next_count; sink_sop <= sink_sop_d;--寄存器输出，避免毛刺 sink_eop <= sink_eop_d; sink_valid <= sink_valid_d; end if; end process; end one;

4、 编辑顶层文件fft256.vhd，具体程序如下： library ieee;

use ieee.std_logic_11.all; entity fft256 is port( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; sink_real : IN STD_LOGIC_VECTOR (7 DOWNTO 0); source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop : OUT STD_LOGIC; source_valid : OUT STD_LOGIC; source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); sink_valid : OUT STD_LOGIC; sink_sop : OUT STD_LOGIC; sink_eop : OUT STD_LOGIC; sink_ready : OUT STD_LOGIC

); end fft256;

architecture one of fft256 is component fft_burst PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; inverse : IN STD_LOGIC; sink_valid : IN STD_LOGIC; sink_sop : IN STD_LOGIC; sink_eop : IN STD_LOGIC; sink_real : IN STD_LOGIC_VECTOR (7 DOWNTO 0); sink_imag : IN STD_LOGIC_VECTOR (7 DOWNTO 0); sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); source_ready : IN STD_LOGIC; sink_ready : OUT STD_LOGIC; source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop : OUT STD_LOGIC; source_valid : OUT STD_LOGIC; source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );

END component;

component ctrl_fft port( reset_n : in std_logic; clk : in std_logic; sink_ready : in std_logic; sink_sop : out std_logic; sink_eop : out std_logic; sink_valid : out std_logic); end component;

signal sink_valid_i,sink_eop_i,sink_sop_i,sink_ready_i : std_logic; begin

sink_valid <= sink_valid_i; sink_sop <= sink_sop_i; sink_eop <= sink_eop_i; sink_ready <= sink_ready_i; u1 : fft_burst port map( clk => clk, reset_n => reset_n, inverse => '0', sink_valid => sink_valid_i,

sink_sop => sink_sop_i, sink_eop => sink_eop_i, sink_real => sink_real, sink_imag => (others=>'0'), sink_error => \"00\ source_ready => '1', sink_ready => sink_ready_i, source_error => source_error, source_sop => source_sop, source_eop => source_eop, source_valid => source_valid, source_exp => source_exp, source_real => source_real, source_imag => source_imag );

u2 : ctrl_fft port map( reset_n => reset_n, clk => clk, sink_ready => sink_ready_i, sink_sop => sink_sop_i, sink_eop => sink_eop_i, sink_valid => sink_valid_i ); end one;

5、 编辑测试台程序fft256_vhd_tst.vhd，程序如下：

-- Vhdl Test Bench template for design : fft256 --

-- Simulation tool : ModelSim (VHDL) --

LIBRARY ieee; USE ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; ENTITY fft256_vhd_tst IS END fft256_vhd_tst;

ARCHITECTURE fft256_arch OF fft256_vhd_tst IS -- constants

constant clk_time_step : time := 1 ns; -- signals signal clk : STD_LOGIC;

signal reset_n : STD_LOGIC;

signal sink_real : STD_LOGIC_VECTOR (7 DOWNTO 0); signal source_error : STD_LOGIC_VECTOR (1 DOWNTO 0);

signal source_sop : STD_LOGIC; signal source_eop : STD_LOGIC; signal source_valid : STD_LOGIC; signal source_exp : STD_LOGIC_VECTOR (5 DOWNTO 0); signal source_real : STD_LOGIC_VECTOR (7 DOWNTO 0); signal source_imag : STD_LOGIC_VECTOR (7 DOWNTO 0); signal sink_valid : STD_LOGIC; signal sink_sop : STD_LOGIC; signal sink_eop : STD_LOGIC; signal sink_ready : STD_LOGIC;

SIGNAL cnttest : std_logic_vector(7 downto 0); COMPONENT fft256 port( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; sink_real : IN STD_LOGIC_VECTOR (7 DOWNTO 0); source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop : OUT STD_LOGIC; source_valid : OUT STD_LOGIC; source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); sink_valid : OUT STD_LOGIC; sink_sop : OUT STD_LOGIC; sink_eop : OUT STD_LOGIC; sink_ready : OUT STD_LOGIC );

END COMPONENT; BEGIN i1 : fft256 PORT MAP (

-- list connections between master ports and signals clk => clk, reset_n => reset_n, sink_real => sink_real, source_eop => source_eop, source_error => source_error, source_exp => source_exp, source_imag => source_imag, source_real => source_real, source_sop => source_sop, source_valid => source_valid, sink_valid => sink_valid, sink_sop => sink_sop,

sink_eop => sink_eop, sink_ready => sink_ready );

reset_n <= '0','1' after 178*clk_time_step; PROCESS BEGIN clk <= '0'; wait for 50*clk_time_step; clk <= '1'; wait for 50*clk_time_step; END PROCESS;

process(reset_n,clk) begin if reset_n='0' then cnttest <= (others=>'0'); elsif rising_edge(clk) then cnttest<=cnttest+1; end if; end process;

sink_real<=\"01111111\" when cnttest(7)='0' else \"10000000\"; --测试信号为方波 END fft256_arch;

6、 设置仿真工具为modelsim，如图1-6所示。点TestBenches按钮进行设置，如图1-7

图1-6设定仿真工具

图1-7 添加测试文件

点击New…，进行进一步设定，如图1-8所示：

图1-8 设定测试文件

对工程进行编译，如果没有错误，选择菜单Tools->Run Eda Simulation Tools->EDA Gate Level

Simulation(针对正式版用户)，试用版可能只能Tools->Run Eda Simulation Tools->EDA RTL Simulation